| Date | Morning | Afternoon | Location |
|---|---|---|---|
| Dec 10 | PYNQ | Meeting room 5+6, Okinawaken Shichoson Jichi Hall (Map), 116-37 Asahimachi, Naha, Okinawa | |
| Dec 11 | Xilinx AWS | Tenbusu Gallery, 3rd floor | |
| HPC-FPGA | RECONF-HPC | Tenbusu hall, 4th floor | |
| INTEL-VINO | Meeting room 1, 3rd floor | ||
| Dec 14 | Embedded ML | Tenbusu hall, 4th floor | |
| ZYNQ-HLS | Meeting room 1+2, 3rd floor | ||
Date: Dec 10, Full day
Location: Meeting room 5+6, Okinawaken Shichoson Jichi Hall (Map), 116-37 Asahimachi, Naha, Okinawa
Topic: Zynq FPGA, Hands-on
Organizer(s): Xilinx
Type: Tutorial WS
Details:
PYNQ is an open-source framework that enables programmers who want to use embedded systems to exploit the capabilities of Xilinx Zynq SoCs. It allows users to exploit custom hardware in the programmable logic without having to use ASIC-style CAD tools. Instead the SoC is programmed in Python and the code is developed and tested directly on the embedded system. The programmable logic circuits are imported as hardware libraries and programmed through their APIs, in essentially the same way that software libraries are imported and programmed.
The framework combines four main elements: (1) the use of a high-level productivity language, Python in this case; (2) Python-callable hardware libraries based on FPGA overlays; (3) a web-based architecture incorporating the open-source Jupyter Notebook infrastructure served from Zynq's embedded processors; and (4) Jupyter Notebook's client-side, web apps. The result is a web-centric programming environment that enables software programmers to work at higher levels of design abstraction and to re-use both software and hardware libraries.
This tutorial will give a hands-on introduction to PYNQ framework using recently introduced PYNQ-Z2 board. It will feature the latest PYNQ release which includes an updated API, an optimized video pipeline, a simplified way of integrating new hardware and drivers into PYNQ, and developing, compiling, and deploying C-language code straight from the Jupyter notebook without opening Xilinx SDK tool.
Note: Attendees will use their laptops to connect to the board.
We would like to ask all attendees to prepare PNYQ-Z2 board and basic accessories (Ethernet cable, MicroUSB cable, SDCard, and Power Supply) in advance and bring it on the day of the workshop.
Please contact FPT18-PYNQ-WS@AVNET.COM for more details.
Note: If the number of applicant exceeds the capacity, further application will not be accepted.
Date: Dec 11, Full day
Location: Tenbusu Gallery, 3rd floor
Topic: AWS, Hands-on
Organizer(s): Xilinx
Type: Tutorial WS
Details: FPGA-based Accelerated Cloud Computing with SDAccel
The increasing computational requirements of next-generation Cloud and High-Performance Computing (HPC) applications are pushing the adoption of accelerated computing based on heterogeneous architectures into mainstream, as traditional CPU technology is unable to keep pace.
Xilinx FPGAs are now available, in two different sizes that include up to eight Virtex® UltraScale+ VU9P, on the Amazon Elastic Compute Cloud (EC2) F1 instances, which are designed to accelerate data center workloads, including machine learning inference, data analytics, video processing, and genomics. Furthermore, Amazon Web Services offers the SDAccel™ Development Environment for cloud acceleration, enabling the user to easily and productively develop accelerated algorithms and then efficiently implement and deploy them onto the heterogeneous CPU-FPGA system.
SDAccel completely automates the step of the hardware design flow, offering an easy to use environment for FPGA application design. It offers the possibility to specify a compute kernel using C and C++ for higher-level algorithmic implementation, or using hardware description languages for RTL designs, while using OpenCL APIs to control run-time behavior.
Attendees will use their laptops to connect to the EC2 F1 instances.
WS WEB »
Date: Dec 11, Half day (morning)
Location: Tenbusu hall, 4th floor
Topic: high-performance computing, emerging workloads
Organizer(s): Argonne National Laboratory, Center for Computational Sciences,University of Tsukuba, RIKEN R-CCS, JLESC, IWFH
Type: Invited talks/panel discussions
Details: Traditionally, high-performance computing (HPC) platforms
have been designed for relatively regular and floating-point
intensive-workloads (e.g., LINPACK). Because of emerging artificial
intelligence, big data, and data analytics requirements, HPC platforms
need to be changed to accommodate such workloads as well as
traditional ones. Since FPGAs have already demonstrated their
acceleration potential for these new HPC requirements, integrating
FPGAs into HPC is a natural step. In this workshop, HPC experts who
have been evaluating FPGAs for HPC will discuss challenges and
opportunities of such integration. Our goal is to initiate new strong
collaborations between FPGA experts and HPC experts. This workshop is
co-held with the International Workshop on FPGA for HPC (IWFH), the
Joint Laboratory on Extreme Scale Computing (JLESC), and the
Field-Programmable Technology Workshop (FPT'18).
Audience participation is highly encouraged.
WS WEB »
Date: Dec 11, Half day (afternoon)
Location: Tenbusu hall, 4th floor
Topic: high-performance computing, programming models, FPGA runtime systems, HPC cluster technologies, network/storage acceleration
Organizer(s): Argonne National Laboratory, Center for Computational Sciences,University of Tsukuba, National Institute of Advanced Industrial Science and Technology
Type: Invited talks/panel discussions
Details: Reconfigurable computers are expected to play an important role in the post-Moore era, offering a true co-design vehicle that could significantly improve both the performance and the energy efficiency of computation. While FPGAs-accelerated systems are becoming practical in the cloud and data centers, FPGAs or reconfigurable computers are still not common in large HPC systems. In this workshop, we will discuss future workloads, programming models, network/storage acceleration and clustering technologies that can enable reconfigurable high-performance computing. Audience participation is highly encouraged.
Date: Dec 11, Half day (afternoon)
Location: Meeting room 1, 3rd floor
Topic: Running Intel OpenVINO Toolkit on Heterogeneous Extensible Robot Open Platform
Organizer(s): Intel
Type: Turorial WS
Details: This workshop explains how to use Intel Open Visual Inference & Neural Network Optimization(OpenVINO). You will learn how to setup and run an FPGA-based OpenVINO face detection or object detection demo design on Intel Heterogeneous Extensible Robot Open Platform(HERO). The workshop will take you through all steps including HERO Platform power-on, FPGA Hardware configuration, Software environment setup, Face Detection or Object Detection code preparation, and execution.
WS WEB »
Date: Dec 14, Half day (afternoon)
Location: Tenbusu hall, 4th floor
Topic: Embedded machine learning discussion with specialists
Organizer(s): David Boland and Philip Leong
Type: Tutorial WS
Details: This workshop will provide a forum to discuss technical challenges and product opportunities for applying
deep learning within embedded systems that take advantage of the energy and latency benefits offered by field programmable
gate arrays (FPGAs).
Date: Dec 14
Location: Meeting room 1+2, 3rd floor
Topic: Hands-on tutorial using a Zynq FPGA
Organizer(s): Digilent
Type: Hands-on tutorial WS
Details: It is a hands-on tutorial using a Zynq FPGA with HLS to design a streaming hardware.
Details (PDF) » (updated November 28)
Hiroki Nakahara, Tokyo Institute of Technology, Japan